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(R)
L6254
12V DISK DRIVE SPINDLE & VCM, POWER & CONTROL "COMBO"
PRODUCT PREVIEW
GENERAL 12V (10%) OPERATION. REGISTER BASED ARCHITECTURE MINIMUM EXTERNAL COMPONENTS BICMOS + VERTICAL DMOS (1.5mm) VCM DRIVER 1.5A DRIVE CAPABILITY 0.9W TOTAL BRIDGE IMPEDANCE AT 25C LINEAR MODE PHASE SHIFT MODULATION (PWM MODE) INSTANTANEOUS, (GLICH FREE) SWITCH BETWEEN THE 2 MODES CLASS AB OUTPUT DRIVERS ZERO CROSSOVER DISTORSION 14 BIT DAC DEFINE OUTPUT CURRENT SELECTABLE TRANSCONDUCTANCE 4 PROGRAMMABLE PARKING VOLTAGE DYNAMIC BRAKE SPINDLE DRIVER 2.0A DRIVE CAPABILITY 0.8W TOTAL BRIDGE IMPEDANCE AT 25C BEMF, INTERNAL OR EXTERNAL, PROCESSING SENSOR-LESS MOTOR COMMUTATION PROGRAMMABLE COMMUTATION PHASE DELAY LINEAR MODE AND CONSTANT TOFF PWM OPERATION MODE INTERNAL FREQUENCY LOCKED LOOP SPEED CONTROL (FLL) BEMF RECTIFICATION DURING RETRACT BUILT-IN ALIGNAMENT&GO START-UP INDUCTIVE SENSING START UP OPTION RESYNCHRONIZATION DYNAMIC & REVERSE BRAKE CONTROLLABLE OUTPUT SLEW RATE OTHER FUNCTIONS 12V AND 5V MONITORING WITH EXTERNAL SET TRIP POINTS AND HYSTERESIS POWER UP/DOWN SEQUENCING LOW VOLTAGE SENSE
BICMOS TECHNOLOGY
TQFP44 (10x10mm) ORDERING NUMBER: L6254
SLUG FOR POWER DISSIPATION THERMAL SHUTDOWN AND PRETHERMAL WARNING
DESCRIPTION The L6254 integrates into a single chip both spindle and VCM controllers as well as power stages. The device is designed for 12V disk drive application requiring up to 2.0A of spindle and 1.5A of VCM peak currents. A serial port with up to 25 MHz capability provides easy interface to the microprocessor. A register controlled Frequency Locked Loop (FLL) allows flexibility in setting the spindle speed. Integrated BEMF processing, digital masking, digital delay, and sequencing minimize the number of external components required. Power On Reset (POR) circuitry is included. Upon detection of a low voltage condition, POR is asserted, the internal registers are reset, and spindle power circuitry is tri-stated. The BEMF is rectified providing power for actuator retraction followed by dynamic spindle braking. The device is built in BICMOS technology allowing dense digital/analog circuitry to be combined with a high power DMOS output stage.
April 1999
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/17
L6254
BLOCK DIAGRAM
FLL_FILTER SPN_COMP PWM/SLEW BRK_CAP SYS_CLK FLL_RES
INDEX
FCOM
CS
CHARGE PUMP
FREQUENCY LOCK LOOP
SPINDLE SEQUENCER
A
VCC
CP
OUT_A CTAP
START-UP SW1 ISO DRIVER RE_SYNC
BEMF PROCESSING ZERO CROSS DETECTION SPINDLE CURRENT CONTROL PWM/LIN
B
OUT_B RSENSE
C
OUT_C ISENSE
SDATA SERIAL INTERFACE
DYNAMIC/ REVERSE BRAKE
SCLK
REGISTERS
VCM CURRENT CONTROL PSM/LIN VCM CALIBRATION
PARKING BEMF RECTIFICATION
A+
VCM_A+ VCC
SDEN
A-
VCM_AVCM_GND
TR_12V TR_5V
SUPPLY FAULT MONITORS
THERMAL SUPPLY 14 BIT VCM DAC REFERENCE VOLTAGE GENERATOR
+ -
A=4 +
SENSE_INSENSE_IN+
POR_DELAY
ERROR_IN
ERROR_OUT
SENSE_OUT
PORB
VDD
DGND
DAC
V12/2
GND
VCM_CAL
D99IN1042
PIN CONNECTION
ERROR_OUT SENSE_OUT POR_DELAY SPN_COMP ERROR_IN
TR-12V
TR_5V
35
AGND
44
43
42 41
40 39
38
37 36
FCOM CTAP PWM/SLEW OUT_C I_SENSE R_SENSE OUT_B GND R_SENSE OUT_A INDEX
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
PORB
34 33 32 31 30 29 28 27 26 25 24 23
VCC
DAC
SW1 FLL_RES VCC VCM_A+ SENSE_INVCM_GND SENSE_IN+ VCM_AVCC CS CP
VCC
SYS_CLK
SDATA
DGND
VDD
FLL_FILTER
SDEN
BRK_CAP
V12/2
SCLK
VCM_CAL
D98IN847
2/17
L6254
PIN DESCRIPTION (Pin Types: D = Digital, P = Power, A = Analog)
N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name FCOM CTAP PWM/SLEW OUT_C I_SENSE R_SENSE OUT_B GND R_SENSE OUT_A INDEX BRK_CAP VCC DGND SYS_CLK SDEN SDATA SCLK VDD V12/2 FLL_FILTER VCM_CAL CP CS VCC VCM_ASENSE_IN+ VCM_GND SENSE_INVCM_A+ VCC FLL_RES SW1 PORB TR_5V POR_DELAY SENSE_OUT ERROR_OUT ERROR_IN TR_12V DAC AGND VCC SPN_COMP Function Output of the Spindle zero cross or Current Sense circuit. Spindle Central Tap used for differential BEMF sensing. RC network sets the Spindle Linear Slew Rate and PWM OFF-Tim e. Spindle DMOS Half Bridge Output and Input C for BEMF sensing. Input to sense the voltage the SPINDLE Sense Resistor. Output connection for the Motor Current Sense Resistor to ground. Spindle DMOS Half Bridge Output and Input B for BEMF sensing. Spindle Ground (Substrate). Output connection for the Motor Current Sense Resistor to ground. Spindle DMOS Half Bridge Output and Input A for BEMF sensing. Input to allow Spindle to be locked to Index (servo) pulse. Storage Capacitor for brake circuit. typically 5.9V. +12V Power Supply for Spindle Power section. Digital Ground. Clock Frequency for system timers and counters. Serial Data Enable. Active high input pin for the serial port enable. Serial Port Data. Input/Output pin for serial data, 8bits of instruction/address followed by 8 bits of data. Open pin is at logic low as an input. Serial Port Data Clock. Positive edge triggered clock input for the serial data. Digital/Analog power supply. +5V nominally. Reference Output for VCM control loop. Typically, half of the VCC except when parking. Speed loop R/C compensation connection used for FLL mode operation. VCM loop offset voltage used for calibration. External Main Charge Pump Capacitor, Typically, Vz+Vcc is about 17.8V External Charge Pump Capacitor. +12V Power Supply for VCM Power section. VCM Power Amplifier negative output terminal. Non inverting Input of the Sense Amplifier for VCM block. Ground for VCM Power section. Inverting Input of the Sense Amplifier for VCM block. VCM Power Amplifier positive output terminal. +12V Power Supply for VCM Power section. Resistor for setting accurate bias current sources for the chip (62K required). External ISOFET driver. Power on Reset Output. Low signal indicates the failure of the supplies. Set Point Input for 5V Supply Monitor ( 2V threshold, 100mV Hysteresis) Capacitor connection to set the Power on Reset Delay (3V threshold, 2A charging) Output of the Sense Amplifier. Output of the Error Amplifier. Inverting Input of the Error Amplifier. Set Point Input for 12V Supply Monitor (2V threshold, 100mV Hysteresis) Output of the VCM DAC. Analog Ground. For bang gap voltage reference. +12V Power Supply for Spindle Power section. External RC network that defines the compensation of the Spindle Transconductance Loop in Linear Mode.
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L6254
ABSOLUTE MAXIMUM RATINGS
Symbol VCC Vdd Vin max Vin min SPINDLE Ipeak VCM Ipeak Ptot (*) Tstg, Tj Maximum Supply voltage Maximum Logic supply Maximum digital input voltage Minimum digital input voltage Spindle peak sink/source output current VCM peak sink/source output current Maximum Total Power Dissipation Maximum Storage/Junction Temperature Parameter Value -0.5 to 14 -0.5 to 6 Vdd +0.3V GND - 0.3V 2.1 1.6 1.7 -40 to 150 Unit V V V V A A W C
THERMAL DATA
Symbol Rth j-case Rth j-amb (*) Parameter Thermal Resistance Junction to Case Thermal Resistance to Junction to ambient Value 20 40 25 with soldered slug Unit C/W C/W C/W
(*) In typical application with multilayer 120x120mm Printed Circuit Board.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vdd Tamb Tj Supply voltage Maximum Logic supply Operating Ambient Temperature Junction Temperature Parameter Value 10.8 to 13.2 4.5 to 5.5 0 to 70 0 to 125 Unit V V C C
ELECTRICAL CHARACTERISTICS (All specifications are for 0 < Tamb < 70C, VCC = 12V; VDD = 5V, FLL_RES = 62k, unless otherwise specified.)
Symbol POWER SUPPLIES VCC IVCC 12V Supply VCC Current SPINDLE + VCM SPINDLE ONLY VCM ONLY Vrectified V dd IVdd VCC Supply Rectified 5V supply 5V supply SPINDLE + VCM SPINDLE ONLY VCM ONLY 4/17 3.5 4.5 6 7 12 10.8 20 7 12 13.2 5.5 13.2 V mA mA mA V V mA mA mA Parameter Test Condition Min. Typ. Max. Unit
L6254
ELECTRICAL CHARACTERISTICS (Continued)
Symbol THERMAL SENSING TSD THYS TEW Shutdown Temperature Hysteresis Early Warning 150 60 TSD-25 180 C C C Parameter Test Condition Min. Typ. Max. Unit
SUPPLY MONITOR V TR VHYS IDLY R on_por VDLY IIN Trip Point Hysteresis Voltage Porb Delay Current Porb Pull Down Ron Porb Dly Threshold Input Current Input Rising Input falling TR_5V, TR_12V > VTR Vpordly = 2V Vdd > 2V and sink 1mA Vpordly = 2V TR_5V, TR_12V > VTR VIN < 4V 2.5 -1 3.0 1.5 1.92 2 100 2 2.5 500 3.5 1 2.08 V mV A V A V kHz
VOLTAGE BOOST VBOOST Fosc Output Voltage Internal Oscillator VCC+5 130 200 VCC+6.3 250
SW1 OUTPUT RGATE VGATE Gate Driver for External Mosfet Off Gate State Voltage for External Mosfet Internal Resistor to CP IO = 1mA VCC = 3.5V 200 0.7 k V
DIGITAL LOGIC LEVELS VIH V IL VOH V OL F SYSCLK VCM, DAC Resolution Differential Linearity 1 LSB Change -Tested By design -1 -0.5 9 Referenced to VCC/2 -5 1 -4 4 5 5 Referenced to VCC/2 14 1 0.5 Bits LSB Bits mV s V % Input Logic "1" Input Logic "0" Output Logic "1" Output Logic "0" System Clock VDD = 5.5V VDD = 4.5V ISOURCE = 20A ISOURCE = -400A 20 Vdd-0.2 0.4 25 2.4 0.5 V V V V MHz
Integral Linearity Midscale Offset TC Convertion Time Full Scale Voltage Full Scale Error VCM, ERROR AMPLIFIER AVOL VOS IIB Open Loop Gain Input Offset Voltage Input Bias Current DC
50 -5 -250 5 250
db mV nA
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L6254
ELECTRICAL CHARACTERISTICS (Continued)
Symbol VICM Vclamp FODB RDS(ON) IO IO(LEAK) Parameter Input Common Mode Range Output Clamp Voltage Unity Gain Bandwidth -1mA < IO < 1mA Lowside/Highside clamp Test Condition Min. VCC/20.5 VCC/2 2.2V 10 Typ. Max. VCC/2+ 0.5 Unit V V MHz A mA
VCM, POWER STAGE Output ON Resistance (Each device) Operating Current Output Leakage Current VCC = 14V Tj = 25C Tj = 125C 0.5 0.8 1.3 1.0
VCM, CURRENT SENSE ANPLIFIER AV VICM VOCM VOS F3dB CMRR PSRR Voltage Gain Input Common Mode Range Output Common Mode Range Output Offset Voltage 3dB Bandwidth Input Common Mode Rejection Power Supply Rejection Ratio 50 60 -3mA < IO < 3mA SENSE_IN () = VCC/2 3.88 -0.3 2 -15 1 4 4.12 VCC+0.3 VCC-2 15 V/V V V mV MHz dB dB
VCM, RETRACT Vpark RETRACT VOLTAGE PKV_1 = 0 & PKV_2 = 0 PKV_1 = 0 & PKV_2 = 1 PKV_1 = 1 & PKV_2 = 0 PKV_1 = 1 & PKV_2 = 1 RT0 = 0 & RT1 RT0 = 0 & RT1 RT0 = 1 & RT1 RT0 = 1 & RT1 =0 =1 =0 =1 725 531 398 1080 320 640 160 320 mV mV mV mV ms ms ms ms
Tretract
Retract Time limited by the internal oscillator 200kHz
SPINDLE, PWM CURRENT SENSE COMPARATOR TDLY Delay to FCOM Out 200 500 ns A mA V/s V/s V/s 40 mVp-p mV
SPINDLE, POWER STAGE RDS(ON) IO IO(LEAK) dVO/dt Output On Resistance (Each device) Start-Up Current Output Leakage Current Output Slew Rate (Linear) Output Slew Rate (PWM) BEMFMIN VHYS Minimum BENF Voltage for Detection Hysteresis VCC = 14V Rslew = 100k Reg#8Eh, Bit 0 = 0 Reg#8Eh, Bit 0 = 1 20 0.2 0.3 10 20 28 15 Tj = 25C Tj = 125C 0.45 0.74 2 1.0 0.5
FLL CHARGE PUMP OUTPUT ILEAK Off State Leakage 0 < Vfll_res , 3V -50 +50 nA
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L6254
ELECTRICAL CHARACTERISTICS (Continued)
Symbol IO Parameter On State Current Test Condition FLL_RES = 62k ICP = "1" ICP = "0" FLL_RES = 62k Min. 22 80 1.18 Typ. 25 100 1.225 Max. 32 120 1.25 Unit A A V A V/V V/s
VRCP
Current Set Voltage
CURRENT SENSE AMPLIFIER IBIAS Av dVo/dt Input Bias Current Voltage Gain Output Slew Rate 3.8 4.0 20 2 4.2
SERIAL PORT Symbol TSCK TCKL TCKH TSDENS TSDENH TDS TDH TSDENL TSDV TSDV SCLK Period SCLK low time SCLK high time Enable to SCLK SCLK to disable Data set-up time before rising edge SCLK Data Hold Time Minimum SDEN Low Time SCLK falling edge (A6) to SDATA valid on READ op. SCLK rising edge (D0-D7) to SDATA Transition on READ op. Parameter Min. 40 15 15 35 20 10 10 50 3 5 10 35 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns
Figure 1. Serial Port Timing Information.
SDEN
SCLK
SDATA
0
A0
A1
A6
D0
D1
D2
D7
1st Byte
2nd Byte
SERIAL PORT WRITE TIMING
SDEN
SCLK
SDATA
1
A0
A1
A6
D0
D1
D2
D7
1st Byte
2nd Byte
SERIAL PORT READ TIMING
D98IN844
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L6254
SERIAL PORT OPERATION The serial port interface is a bi-directional port for reading and writing programming data from/to the internal registers of this device. For data transfers SDEN* is brought high, serial data is presented at the SDATA pin, and a serial clock is applied to the SCLK pin. After the SDEN* goes high , the first 16 pulses applied to the SCLK pin will shift the data presented at the SDATA pin into an internal shift register on the rising edge of each clock. An internal counter prevents more than 16 bits from being shifted into the register. The data in the shift register is latched after the 16th SCLK pulse. If less than 16 clock pulses are provided before SDEN* goes low, the data transfer is aborted. All transfers are shifted into the serial port LSB first. The first byte of the transfer is for R/W and address and instruction information. The first bit is R/W instruction bit, 0 is for WRITE and 1 is for READ. Following 7 bits are Address. Figure 2. Serial Port Data Transfer Format.
SDEN
SDATA
INSTRUCTION, 1 BIT ADDRESS, 7 BITS
DATA, 8 BITS
SCLK
D98IN845
INTERNAL REGISTER DEFINITION Reg: Name: Type: Address: 0 VCM DAC (High) Register Write only 0Eh
BIT 0 1 2 3 4 5 6 7 VDAC BIT8 VDAC BIT9
LABEL VCM DAC bit 8 VCM DAC bit 9 VCM DAC bit 10 VCM DAC bit 11 VCM DAC bit 12
DESCRIPTION
VDAC BIT10 VDAC BIT11 VDAC BIT12 VDAC BIT13 PSM/LINEAR VCM_CAL
MSB resistor ladder of the 14 bit VCM DAC Selects Voice Coil PSM or Linear Output Current Control. 1=PSM 0=Linear. VCM calibration. 1 = Enables VCM control circuits and tristates VCM power transistors.
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L6254
INTERNAL REGISTER DEFINITION VCM DAC (High and Low) Registers Bit 0 through 5 of the VCM DAC (High) Registers and bit 0 through 7 of the VCM DAC (Low) Registers control the absolute value of the voice coil current. Bit is the sign bit, controlling the current direction. All the 13 bits are part of a resistor divider network. Note. It is required to write on register 1 to make effective changes on register 0. Reg: Name: Type: Address: 1 VCM DAC (Low) Registers Write only 1Eh
BIT 0 1 2 3 4 5 6 7 VDAC BIT0 VDAC BIT1 VDAC BIT2 VDAC BIT3 VDAC BIT4 VDAC BIT5 VDAC BIT6 VDAC BIT7
LABEL
DESCRIPTION LSB resistor ladder of the 14 bit VCM DAC VCM DAC bit 1 VCM DAC bit2 VCM DAC bit3 VCM DAC bit4 VCM DAC bit5 VCM DAC bit6 VCM DAC bit7
Reg: Name: Type: Address:
2 Spindle Control Register Write only 2Eh
BIT 0 1 2 3 4 5 6 7
LABEL INCRE_SEQ START_UP R_SEQ RUN SPIN_EN MEC/ELEC PWM/LINEAR EXT/INT
DESCRIPTION A 0 to 1 transition of this bit increments the spindle Sequencer. 1 = Spindle Internal start up, 0 = Spindle External start up Reset Spindle sequencer. 1 = Reset sequencer to phase 1. 1 = Start Spindle ALIGN & GO, 0 = Reset Spindle control logic. Enable Spindle section. 1 = Enable, 0 = Disable. Specifies electrical or mechanical cycle for Spindle FLL control. 1=Electrical, 0 = Mechanical. Selects Spindle PWM or Linear Output Current Control. 1 = PWM, 0=Linear. External or internal Spindle loop feedback. 1 = external feedback via index pin.
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L6254
INTERNAL REGISTER DEFINITION
Reg: Name: Type: Address:
3 Spindle Delay Register Write only 3Eh
BIT 0 1
LABEL MASK_TIME MIN2
DESCRIPTION Spindle BEMF Mask Time. 0 = 15 degree, 1 = 7.5 degree Control Spindle PWM on time Min 1 0 Min2 0 1 0 1 Min. on Time 5.9s 1.4s 12s 5.21s
2
MIN1
0 1 1
3 4 5 6 7
8_12_POLE SD3 SD2 SD1 SD0
Selects 8 or 12 pole motors. 1 = 8 pole, 0 = 12 pole. Spindle commutation delay MSB Spindle commutation delay bit Spindle commutation delay bit Spindle commutation delay LSB
SPINDLE PHASE DELAY SD3-0 set the phase delay from BEMF zero crossing to the next commutation. The 30 theoretical degree value can be changed to compensate for switching and other delays that are always present. The delay adjustment range is from 1.875 through to 30 electrical degrees in 1.875 degree increments.
Reg: Name: Type: Address:
4 FLL Coarse Counter Register Write only 4Eh
BIT 0 1 2 3 4 5 6 7 C4 C5 C6 C7 C8 C9 C10 C11
LABEL
DESCRIPTION Bit 4 of Spindle FLL Coarse Counter Bit 5 of Spindle FLL Coarse Counter Bit 6 of Spindle FLL Coarse Counter Bit 7 of Spindle FLL Coarse Counter Bit 8 of Spindle FLL Coarse Counter Bit 9 of Spindle FLL Coarse Counter Bit 10 of Spindle FLL Coarse Counter MSB of Spindle FLL Coarse Counter
10/17
L6254
INTERNAL REGISTER DEFINITION
Reg: Name: Type: Address:
5 FLL Coarse/Fine Counter Register Write only 5Eh
BIT 0 1 2 3 4 5 6 7 F8 F9 F10 2/3_PHASE C0 C1 C2 C3
LABEL
DESCRIPTION Bit 8 of Spindle FLL Fine Counter Bit 9 of Spindle FLL Fine Counter MSB of Spindle FLL Fine Counter 1 = 2 Phase Brake, 0 = 3 Phase Brake LSB of Spindle FLL Coarse Counter Bit 1 of Spindle FLL Coarse Counter Bit 2 of Spindle FLL Coarse Counter Bit 3 of Spindle FLL Coarse Counter
Reg: Name: Type: Address:
6 FLL Fine Counter Register Write only 6Eh
BIT 0 1 2 3 4 5 6 7 F0 F1 F2 F3 F4 F5 F6 F7
LABEL
DESCRIPTION LSB of Spindle FLL Fine Counter Bit 1 of Spindle FLL Fine Counter Bit 2 of Spindle FLL Fine Counter Bit 3 of Spindle FLL Fine Counter Bit 4 of Spindle FLL Fine Counter Bit 5 of Spindle FLL Fine Counter Bit 6 of Spindle FLL Fine Counter Bit 7 of Spindle FLL Fine Counter
11/17
L6254
INTERNAL REGISTER DEFINITION Reg: Name: Type: Address: 7 Spindle Status Register Read only 7Eh
BIT 0
LABEL THERMAL
DESCRIPTION Thermal Shutdown = 0 indicates that the chip temperature has exceeded 160C. The bit will reset (=1) when the temperature falls below 130C. When Thermal Shutdown =0, the spindle logic will tristate both high and low side drivers, protecting the output circuitry. Thermal Shutdown Warning =0 indicates that the chip temperature is approximately 25C before the device goes in thermal shut down. 0 = A sequential Spindle BEMF has not been detected 1 = Rapid deceleration of the Spindle motor or High frequency on FCOM signal. Mask Time toggled to "0" indicates that the Spindle BEMF is masked. 0 = Indicates error Spindle speed > 16msec/sample, either electrical or mechanical. 0 indicate that the Spindle is in the Internal Start-Up Align Phase. 0 indicate that the Spindle is in the Internal Start-Up Go Phase.
1 2 3 4 5 6 7
THERM_WARN ROTOR_STUCK FAULT MASK_TIME ERROR_LOCK ALIGN GO
Reg: Name: Type: Address:
8 Spindle FLL Register Write only 8Eh
BIT 0 1 2 3 4 5 6 7 ISNS IL1 IL0 CPL CPH "IL0" 0 1 0 1 0 1 0 1 12/17 ICP
LABEL SSLEW
DESCRIPTION Spindle PWM (chopping) Slew Rate. 0 = 10VS, 1 = 20VS Spindle FLL Charge pump current. 1= 25A, 0 = 100A. Unused. Set = 0. 1 = Puts output of the Spindle sense amplifier on FCOM pin and changes limit to roughly 1/3 of normal. Adjust maximum voltage on Spindle Rsense Adjust maximum voltage on Spindle Rsense 1 = Spindle FLL Charge pump low 1 = Spindle FLL Charge pump high "IL1" 0 0 1 1 0 0 1 1 "ISNS" 0 0 0 0 1 1 1 1 V(I_SENSE) LIMIT (10%) 0.45V 0.50V 0.55V 0.75V 0.15V 0.20V 0.25V 0.30V
L6254
INTERNAL REGISTER DEFINITION
Reg: Name: Type: Address:
9 System Control Register Write only 9Eh
BIT 0 1 2 3 4 5 6 7 PKV_1 PKV_2 VR RT0 (*) DOUBLE VCM_EN RT1 (*) RETRACT
LABEL VCM Parking Voltage VCM Parking Voltage
DESCRIPTION
1 = connects internal VR reference (2V) to level shift Opamp (for Vcm calibration). VCM Retract Time 1 = Spindle Internal Start-Up Align and Energization time doubled. Enable VCM section. 1 = Enable, 0 = Disable. VCM Retract Time 1= VCM retract
"PKV_1" 0 0 1 1 "RT0" 0 0 1 1
"PKV_2" 0 1 0 1 "RT1" 0 1 0 1
"PARKING VOLTAGE" 0.725V 0.531V 0.398V 1.080V "RETRACT TIME" 320ms 640ms 160ms 320ms
(*) When program Retract Time (RT0 and RT1), Bit 2 REG#8Eh must be always written to 0.
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L6254
INTERNAL REGISTER DEFINITION
Reg: Name: Type: Address:
10 Test Control Register Write only AEh
BIT 0 1 2 3 4 5 6 7 VB/DIS FLL_OUT
LABEL Unused. Set = 0 Unused. Set = 0 Unused. Set = 0 Unused. Set = 0
DESCRIPTION
1 = Spindle Mech/Elec (see bit 5 register 2) output, 0 = Spindle zero crossing output. Spindle Reverse Brake command. 1 = Brake. "0" has to be reinserted to enable the spindle start up. Unused. Set = 0 1 = Disable Vboost
REV_BRAKE
Reg: Name: Type: Address:
11 VCM Control Register Write only BEh
BIT 0 1 2 3 4 5 6 7 VCMS VCMH SLEEP COMSLEW
LABEL
DESCRIPTION VCM PSM (chopping) Slew Rate. 0 = 10V/s, 1 = 20V/s 1 = Forces VCM outputs to be High in PSM mode. Unused (for future power saving mode). Spindle PWM (phase commutation) Slew Rate. 0 = 30Vs, 1 = 2Vs. Unused. Set = 0 Unused. Set = 0 Unused. Set = 0 Unused. Set = 0
14/17
L6254
INTERNAL REGISTER DEFINITION
Reg: Name: Type: Address:
12 Chip ID Register Read only FFh
BIT 0 1 2 3 4 5 6 7 ID_REV_0 ID_REV_1 ID_REV_2 ID_REV_3 ID_REV_4 ID_REV_5 ID_REV_6 ID_REV_7
LABEL Minor Revision Bit 0. Minor Revision Bit 1. Minor Revision Bit 2. Minor Revision Bit 3. Minor Revision Bit 0. Minor Revision Bit 1. Minor Revision Bit 2. Minor Revision Bit 3.
DESCRIPTION
Figure 3. Application Circuit.
12V_VCC STN4NE03 0.3(1W) 22F 16V (1) 1F 1N4148 47nF 1N4148 CS CP SW1 100nF POR_DELAY 100nF VCC 13,43 24 23 33 36 21 12 32 FLL_RES 62K VCC INDEX FCOM PORB 4.7K 5V_VDD PORB 15 18 17 35 22 VCM_CAL 20 V12/2 DAC 10K 41 ERROR_IN 39 ERROR_OUT 62K 1nF 38 SENSE_OUT 10K 37 28 VCM_GND
D99IN1049
VCC
CTAP
OUT_A
OUT_B
OUT_C
RSENSE 6,9
ISENSE 5
CTAP 2
OUT_A 10
OUT_B 7
OUT_C 4 26 27 30 29 VCM_ASENSE_IN+ 0.25(1W) VCM_A+ SENSE_INFLL-FILTER 1F VCM_A+ 620K
VCM_A-
2.2F
BRK_CAP
220pF(3) 51K 5K(4)
PWM/SLEW DGND
3 14 44 42
100nF
25,31 11 1 34
VCC INDEX FCOM
SPN_COMP 10nF(4) AGND 12V_VCC 5K(4) 15K 5V_VDD 20K 22F 16V (1) 100nF TR_12V
40
GND VDD
8 19
SYS_CLK SCLK SDATA SDEN
SYS_CLK SCLK SDATA SDEN
TR_5V 18.2K
16
Voice Coil Ground Power Ground
Analog Ground Digital Ground
(1) This capacitor must be Tantalum (2) Place these components close to thedevice (3) Do not mount this component if Spindle Linear mode is used (4) Do not mount this component if Spindle Pwm mode is used
15/17
L6254
mm MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.30 0.09 12.00 10.00 8.00 0.80 12.00 10.00 8.00 0.60 1.00 0.75 0.018 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 0.002 0.053 0.012 0.004 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.024 0.039 0.030 0.055 0.014 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.018 0.008
DIM.
OUTLINE AND MECHANICAL DATA
TQFP44 (10 x 10)
0(min.), 3.5(typ.), 7(max.)
D D1 A1
33 34 23 22
0.10mm .004 Seating Plane
A A2
E1
B
44 1 11
12
E
B
e
L
C
K
TQFP4410
16/17
L6254
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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